Complementary metal-oxide-semiconductor (CMOS) technologies have been used for manufacturing semiconductor devices. CMOS technologies may include gate-first processing technologies and gate-last processing technologies.
In a gate-first process, a gate is deposited on a gate dielectric layer before source and drain implantation is performed. The gate-first process may involve relatively simple steps. Nevertheless, in the gate-first process, after the gate has been formed, the gate has to endure substantial heat during subsequent processing steps, such as annealing. The heat imposed on the gate may result in a drift of the threshold voltage Vt of the transistor associated with the gate, and the electrical performance of the transistor may be unsatisfactory.
In a gate-last process, a dummy gate (such as polycrystalline silicon) and a source region and a drain region are first formed. The dummy gate is then taken out to form a gate trench. Subsequently a suitable metal fills into the gate trench to form a metal gate. Thus the gate electrode avoids the heat produced during forming the source region and the drain region. As a result, a drift of the threshold voltage Vt of the transistor associated with the gate may be minimized, and the electrical performance of the transistor may be satisfactory.
In a semiconductor device, such as a storage unit, a contact hole may be required for connecting the source electrode or the drain electrode with an upper metal wire. Because of the limited space between the gates, a self-aligned contract hole may be required.
A self-aligned contact hole may be formed in a gate-first process that comprises the following steps: forming a gate on a semiconductor substrate with an oxide layer being disposed between the gate and the substrate; forming spacers at both sides of the gate; forming a protection layer on the gate to cover the gate; forming a source and a drain on the semiconductor substrate; forming a barrier layer on the semiconductor substrate, on outer sides of the spacers, and on the protection layer (which covers the gate), the barrier layer being formed of silicon nitride (SiN); forming an dielectric layer on the silicon nitride; forming a mask layer comprising a pattern of a self-aligned contact hole on the dielectric layer; and etching the dielectric layer to form the self-aligned contact hole having a bottom between two adjacent gates according to the contact hole pattern.
In the gate-first process, the etch selectivity ratio between the SiN barrier layer and the dielectric layer may be substantially high. Therefore, during the etching process in fabricating the contact hole, the loss of the SiN barrier layer may be minimized. As result, a sufficiently thick insulation layer (which may include a substantial portion of the remaining SiN barrier layer) may be formed between the gate and the contact hole. Nevertheless, as discussed above, the gate-first process may result in satisfactory electrical performance of the semiconductor device.
On the other hand, if a self-aligned contact hole is formed in a gate-last process, the top opening of the self-aligned contact hole may be very close to the metal gate. As a result, short-circuit between the self-aligned contact hole and the metal gate may occur. In particular, the risk of short-circuit between the contact hole and the gate may be aggravated due to misalignment during a photolithography and/or etch process in making the self-aligned contact hole.
The above information disclosed in this Background section is for enhancement of understanding of the background of the invention. The Background section may contain information that is not known on one of ordinary skill in the art.